Electronic devices, such as mobile phones, personal computers, personal digital assistants, and many others, utilize processors, memories, input/output (I/O) and other digital devices in order to provide their designed functionality to end users. These various digital devices are connected to one another using interconnects (also sometimes referred to as “busses” or “interfaces”), which convey data, signals and commands between or among the various devices.
Some interconnects, like many other electrical devices, are specified by standards. For example, in the Mobile Industry Processor Interface Alliance (MIPI), several standards are defined. One of these standards is called UniPro (Unified Protocol), which is aimed at chip-to-chip networks using high-speed serial links. UniPro is defined to be a general purpose protocol that solves the general interconnect problems, such as error handling, flow control, routing or arbitration. UniPro is intended to increase the flexibility of phone manufacturers by mixing and matching chips with different functionalities, potentially from different vendors for easy creation of new devices.
For high-speed serial interfaces, interface testing typically consists of two parts, PHY testing of the electrical behaviour of the interface and protocol testing of the protocol behaviour of the interface. PHY testing is typically done using logic analyzers which can produce and capture signals with a detailed timing accuracy, and analyze whether the captured signals match the desired behaviour. Protocol testing is typically done assuming the PHY works, and uses an enhanced protocol implementation at the tester side, which inserts specific protocol patterns that can drive the Device under Test (DuT) into various corner cases.
The reason for this split in the testing process is the different nature of the two testing phases. The PHY testing needs electrical and timing accuracy. However, a tester for PHY testing is not capable of handling protocol interaction, which could be fairly complex. Protocol testing needs a high level of interactivity, and the ability to generate “ill” patterns to drive the DuT in various corner cases. However, a tester for protocol testing is not capable of electrical or timing accuracy, and assumes a working PHY for raw data transport. These types of interface testing can be used for various purposes, including testing for debug, conformance testing and production testing.
Currently, PHY testing is done using loopback. This is possible as the existing high-speed interfaces, such as PCI Express, HyperTransport or RapidIO, are symmetrical. Symmetrical, in this context, means that the two directions of a link are used with the same set of parameters, such as the number of lanes, the data rates, the encoding, etc. As a result of this symmetry of these existing interfaces or interconnects, the data sent on the link from the tester to the DuT (UpLink) can be streamed back to the tester using the other direction of the link (DownLink).
The loopback mechanism is a simple yet effective means to test a high-speed interface with a symmetrical usage of the incoming and the outgoing parts of the link. However, recently, interfaces have emerged in which the usage of the UpLink and DownLink is asymmetrical. Examples of such interfaces are UniProSM [UniPro] and LLI, which are standardized in the MIPI Alliance [MIPI]. UniProSM offers support for both D-PHY [D-PHY] and M-PHY [M-PHY] Physical Layers, also defined in the MIPI Alliance. LLI is built on top of M-PHY.
Both UniProSM and LLI allow an asymmetrical usage of the link in the sense that the UpLink and DownLink may have different static capabilities (e.g., different number of lanes, different speed capabilities). Moreover, even if the UpLink and DownLink have the same static capabilities, they may be configured differently (e.g., different number of lanes, different speed or power modes).
When the interface is asymmetrical, the loopback does not provide enough testing coverage anymore. For example, if the UpLink only has low-speed capabilities, and the DownLink offers high-speed capabilities, the high-speed cannot be effectively tested because the data cannot be provided at the speed required by the DownLink. Similar speed mismatches also show up when the UpLink has fewer lanes than the DownLink.
One other issue with an asymmetrical usage of the link is that the DownLink requires individual configuration. This is, it cannot follow the configuration of the UpLink like in the symmetrical link case. Therefore, the DuT has to offer means to have its DownLink PHY individually configured (e.g., the power mode), and the Tester has to have the means to configure the DuT. This PHY configuration has to be simple enough to be usable with a standard logical analyzer, which does not support complex protocol interaction.
Accordingly, it would be desirable to provide methods, nodes and systems for interconnect link testing, e.g., for M-PHY links in UniPro systems.